Deck | Reader | CPU | Output | |
---|---|---|---|---|
Instruction Decoder Instruction Register: Opcode: Operand: Accumulator: |
This is "forked" from
https://www.cs.drexel.edu/~bls96/museum/cardsim.html
(description) and edited by JamesNewton@MassMind.org via
https://stackblitz.com/edit/cardiac-computer-sim?file=script.js
to add an SVG block diagram which was made via:
https://svgedit.netlify.app/editor/index.html
and is now animated in the simulator to assist in the understanding of the user. The source code is at
https://github.com/JamesNewton/JamesNewton.github.io/edit/master/cardiac